Title:
シリアライザ装置
Document Type and Number:
Japanese Patent JP6687392
Kind Code:
B2
Abstract:
A serializer device (1) includes a first latch unit (11), a second latch unit (12), a conversion unit (13), a frequency division unit (14), a load signal generation unit (15), a phase difference detection unit (16), and a reset instruction unit (17), and has a simple configuration and can reduce a bit error rate at an early stage. The phase difference detection unit (16) detects a phase difference between a first clock (CLK1) applied to the first latch unit (11) and a third clock (CLK3) applied to the second latch unit (12). The reset instruction unit (17) outputs a reset instruction signal (RSTn) to the frequency division unit (14) when the phase difference is not within a target range.
Inventors:
Yusuke Fujita
Toshikazu Kubo
Yoshinobu Oshima
Toshikazu Kubo
Yoshinobu Oshima
Application Number:
JP2016002722A
Publication Date:
April 22, 2020
Filing Date:
January 08, 2016
Export Citation:
Assignee:
THine Electronics Inc.
International Classes:
H04L7/00; H03K5/00; H03K5/26; H03M9/00
Domestic Patent References:
| JP6244739A | ||||
| JP6104741A | ||||
| JP2009118449A | ||||
| JP10107786A | ||||
| JP2000315147A |
Foreign References:
| WO2004040835A1 |
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yoshiki Kuroki
Masatoshi Shibata
Yoshiki Kuroki
Masatoshi Shibata