PURPOSE: To perform correct series and parallel conversion even when the delay time of an element forming a circuit and its variance are large by converting a data sequence inputted in series into parallel data while reducing the speed.

CONSTITUTION: 1/2 Frequency dividers 1 and 2 generate clock signals CLK2 and CLK3 from a clock signal CLK1. A decoder 1 supplied with the CLK2 and CLK3 generates CLK4∼CLK7. Then, registers FF1∼FF7 controlled with the CLK4∼ CLK7 latch data SD1 inputted in series. Outputs from those FF1∼FF4 are supplied to a register FF5 controlled with the CLK3 and made into parallel data. Thus, the series and parallel conversion is carried out even when the delay time of the element forming the circuit and its variance are large.