PURPOSE: To simplify the constitution of a series-parallel converting circuit of digital data, by performing a series-parallel conversion of data of many bits with use of a small number of signal lines.

CONSTITUTION: When an output of data is started, an R/W signal is first set at 0V. Then a clock signal varies 16 times to 0V, and the data bit to be written synchronously with said clock signal from a control circuit part 31 is sent in series to a data signal line 42. In this case, a gate circuit 36 has its output of a high impedance (cut-off state) owing to the R/W signal of 0V. An output shift register 34 is driven by a shift clock given from an OR circuit 39 to store 15 data bits of the line 42.