Title:
SERIES-PARALLEL DATA CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JPS59103424
Kind Code:
A
Abstract:
Serial to parallel conversion circuitry achieves phase synchronization and signal bit sampling of received asynchronous serial data through use of a gate enable delay line oscillator having a selected response time, and selectably enabled in the presence of the received serial data to provide a sampling clock signal for shifting the serial data into register for parallel formatting at a frequency equal to the line frequency.
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Inventors:
GUREGORII JIYON MAKUBURIEN
Application Number:
JP20464183A
Publication Date:
June 14, 1984
Filing Date:
October 31, 1983
Export Citation:
Assignee:
UNITED TECHNOLOGIES CORP
International Classes:
H03M9/00; H03K3/03; H04L5/24; H04L7/02; H04L13/10; H04L25/40; H04L25/45; (IPC1-7): G06F5/04; H03K13/256; H04L7/02; H04L13/14; H04L25/45
Domestic Patent References:
| JP42004208A | ||||
| JPS5622134A | 1981-03-02 | |||
| JP40020735A | ||||
| JPS5521639A | 1980-02-15 |
Attorney, Agent or Firm:
Akashi Masatake