Title:
SET REST FLIP-FLOP CIRCUIT
Document Type and Number:
Japanese Patent JPS61276414
Kind Code:
A
Abstract:
PURPOSE: To keep the duty ratio constant and to prevent malfunction of the title circuit using a delay circuit to retard a leading time of a waveform thereby matching the leading time to the delay time of the trailing time.
CONSTITUTION: An output section of gate circuits 1, 2 constituting an FF is provided with a delay means comprising a diode D1 or D2 with fast response speed and a resistor R1 or R2. Resistance value of the resistors R1, R2 is selected to use a difference from charge-time by the diodes thereby adjusting the signal delay time. Thus, the signal duty ratio is kept constant so as to prevent malfunction.
More Like This:
| JPH09223948 | SHIFT REGISTER CIRCUIT AND IMAGE DISPLAY DEVICE |
| JPH01265608 | FLIP-FLOP CIRCUIT |
Inventors:
MIYAKI YUJI
ENDO TAKEMI
OKUMA YOSHINORI
SUZUKI KAZUHIRO
YAKO HIROSHI
ENDO TAKEMI
OKUMA YOSHINORI
SUZUKI KAZUHIRO
YAKO HIROSHI
Application Number:
JP11802885A
Publication Date:
December 06, 1986
Filing Date:
May 31, 1985
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03K3/037; (IPC1-7): H03K3/037
Attorney, Agent or Firm:
Sadaichi Igita