PURPOSE: To miniaturize the circuit constitution and to eliminate the change for each clock of the parallel output by constituting each register of three latches.

CONSTITUTION: Data inputted to a first latch 31 of a register 1 is sent to second and third latches 32 and 33. The second latch 32 transfers this serial data to a register 2 in the next stage, and the third latch 33 takes in sent data at the time of application of a signal to an input enable POE and outputs data in parallel. Until the next signal is applied to an output enable, the same data is held. Thus, the circuit scale is reduced by 3/4 in comparison with a conventional shift register, and held data is used in the stable state until the signal is next applied to the output enable.