PURPOSE: To prevent malfunction of shifting operation caused by skewness of a clock signal, in a shift register circuit which operates with one phase clock.

CONSTITUTION: A flip flop circuit 1 is constituted so that a flip flop circuit 2 is connected in series to a tristate buffer circuit 5 which is operated with a low enable signal. A flip flop circuit 2 is constituted so that a latch circuit 3 which is operated with the low enable signal is connected in series to a latch circuit 4 which is operated with a high enable signal. Consequently, even if skewness of a clock signal occurs in the flip flop circuit, since sufficient time for timing of half period of the clock signal is obtained, reliable shifting operation can be performed.