Title:
SHIFT REGISTER, CONTROL METHOD OF THE REGISTER, DATA LINE DRIVING CIRCUIT, SCANNING LINE DRIVING CIRCUIT, ELECTROOPTICAL PANEL AND ELECTRONIC EQUIPMENT
Document Type and Number:
Japanese Patent JP3692846
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an X shift register which surely operates even though the driving capability of clock signals is lowered.
SOLUTION: An X shift register 110 is provided with a shift register 111 in which shift register unit circuits Ua1 to Uan+2 are cascade connected, and a clock control circuit 112 in which control unit circuits Ub1 to Ubn+2 are cascade connected. The circuits Ub1 to Ubn+2 supply X clock signals XCK and inverse X clock signals XCBK to the circuits Ua1 to Uan+2 during an interval in which either one of the input or the output signals of the corresponding circuits Ua1 to Uan+2 become active. Moreover, the output signals of the circuits Ua1 to Uan+2 are reset for every field by reset signals SINT.
Inventors:
Shin Fujita
Application Number:
JP20654799A
Publication Date:
September 07, 2005
Filing Date:
July 21, 1999
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G11C19/00; G02F1/133; G09G3/20; G09G3/36; (IPC1-7): G09G3/36; G02F1/133; G09G3/20; G11C19/00
Domestic Patent References:
| JP10039823A | ||||
| JP10199284A | ||||
| JP5028789A | ||||
| JP3147598A | ||||
| JP2000259132A | ||||
| JP2000269787A | ||||
| JP11085111A | ||||
| JP57158095A |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Osamu Suzawa
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