PURPOSE: To attain a shift operation in a parallel input mode and to realize a parallel input operation having a sampling function by setting properly a P/S signal and a control signal.

CONSTITUTION: An FF1 having a multi-stage cascade is provided together with a gate 2 which is controlled by a parallel/serial switching P/S signal and opens and closes the input given from a parallel input terminal, and a clock input means which is set to the FF1 to shift the input given from the series input terminal. A counter 8 counts the input pulses of the clock up to the number obtained by adding 1 to the stage number (n) of the FF1. The gate 2 is controlled with the count-up output of the counter 8, the output of an AND circuit 9 which supplies the P/S signal, and the output of an OR circuit 10 which supplies a control signal which performs switching between the normal parallel input operation and a parallel input operation having a smapling function. Therefore it is possible to select an input mode by setting the high and low levels of the control signal and the P/S signal.