PURPOSE: To prevent the racing phenomenon by operating an even FF row and an odd FF row synchronously with each other by the first and the second synchronizing signals which are obtained by 1/2 frequency division of a synchronizing signal and are different in phase from each other.

CONSTITUTION: Reference clock signals and - are subjected to 1/2 frequency division to generate clock signals CLK and -CLK which are different in phase by 180° and have the double period. The clock signal -CLK is inputted to master- side FFs 11 and 31 of masterslave FFs 10 and 30 forming the odd FF row, and the clock signal CLK is inputted to slave-side FFs 12 and 32. In contrast with the odd FF row, the clock signal CLK is inputted to master-side FFs 21 and 41 of master-slave FFs 20 and 40 forming the even FF row, and the clock signal -CLK is inputted to slave-side FFs 22 and 42. Since these clock signals CLK and -CLK do not overlap, the racing phenomenon does not occur.