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Title:
SIGMOID FUNCTION ARITHMETIC UNIT AND ITS COMPUTING METHOD
Document Type and Number:
Japanese Patent JPH06203058
Kind Code:
A
Abstract:

PURPOSE: To perform calculation with high accuracy and at high speed without complicating hardware constitution.

CONSTITUTION: The square of the output ex of a register 25 is taken on a multiplier 25 when it is -x2≤x<-x1, and a result e2x is held with the register 25. thence, e2x, e4x, e6x,... are outputted from the multiplier 24 by repeating processing to calculate the product of the output of the multiplier 24 and that of the register 25, and the products -e2x, +e4x, -e6x,... of the output of the multiplier 24 and that of a ROM 30 are calculated by a multiplier 13 in parallel with the above processing, and furthermore, the sum 1 of the output 1 of a ROM 34 and the output 0 of a constant setting circuit 32 is outputted to an adder/substractor 14 first in parallel with the above processing, thence, the sum of the output of the multiplier 13 and that of the adder/subtractor 14 is calculated repeatedly, thereby, g(x)=1-e2x+e4x, -e6x,... is outputted from the adder/subtractor 14, thence, the product of the output g(x) of the adder/ subtractor 14 and the output e2x of the register 25 is calculated by the multiplier 13, and it is outputted as a value of sigmoid function.


Inventors:
HIROSE YOSHIO
Application Number:
JP34762092A
Publication Date:
July 22, 1994
Filing Date:
December 28, 1992
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F15/18; G06F17/17; G06N3/06; G06N99/00; (IPC1-7): G06F15/353; G06F15/18
Attorney, Agent or Firm:
Matsumoto Shinkichi



 
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