Title:
【発明の名称】信号遅延回路
Document Type and Number:
Japanese Patent JP2795356
Kind Code:
B2
Abstract:
A signal delay circuit includes a driving circuit for driving an output signal with a voltage swing voltage between a supply voltage and a ground voltage. The signal delay circuit further includes a varactor load which is coupled to the output signal and has a capacitance which increases according to the supply voltage within a variation range of the supply voltage. The varactor load keeps the delay characteristic of the signal propagation circuit independent of the change of the supply voltage, thereby ensuring high speed operation and improved reliability of the CMOS semiconductor integrated circuit.
Inventors:
SHIN INSHO
Application Number:
JP29517090A
Publication Date:
September 10, 1998
Filing Date:
October 31, 1990
Export Citation:
Assignee:
SANSEI DENSHI KK
International Classes:
G11C11/4076; H03K4/02; H03K5/13; H03K19/003; H03K5/00; (IPC1-7): H03K5/13; H03K4/02; H03K19/003
Domestic Patent References:
| JP25465A | ||||
| JP59214319A | ||||
| JP3171812A |
Attorney, Agent or Firm:
Hiroaki Sakai