PURPOSE: To improve measurement resolution without increasing the frequency of a clock signal by delaying target signals so that the signals are at nearly equal interval within the period of the clock signal.

CONSTITUTION: A crystal oscillator 11 generates a clock signal CK and a delay line 12 delays a detection signal (target signal) inverted by an inverter gate 24 in four stages. Signals A2-A5 delayed for a detection signal A1 become signals which are delayed at nearly equal interval within one cycle of the clock signal CK. Signals B1-B5 are outputted from AND gates 13-17. A main counter 18 counts the signal B1 and first to fourth sub-counters 19-22 count the signals B2-B5. A computer 23 reads the count values of the main counter 18 and the sub-counters 19-22 and executes averaging. In this manner, by counting with target signals which are delayed at nearly equal intervals within one cycle of the clock signal CK and averaging the counted values, the difference within the clock cycle can also be measured.