PURPOSE: To reduce a signal monitor circuit in scale and to transfer it at a high speed by detecting that the state of the transfer request reception signal is shifted every time the timing signal is active.

CONSTITUTION: A signal monitor circuit is provided with an edge detecting circuit 4 which detects the leading and trailing edges of the state shift of a request reception input signal 11 and outputs an edge detecting signal 12, a counter 1 which counts the signals 12, a latch circuit 2 which the contents of the counter 1 with the signal 7 obtained by delaying the timing signal 16 by a delay circuit 6, a ocmparator 3 which compares the contents between the counter 1 and the circuit 2 and outputs the comparison result 15, and a latch circuit 5 which refers to the result 15 with the signal 16 and outputs the output signal 18. This signal 18 shows whether the signal 11 is shifted or not once or more in a period during which the next timing signal 16 is made active after the first signal 16 is made active.