Title:
信号処理回路、それを用いた分散メモリ、ＲＯＭおよびＤＡＣ
Document Type and Number:
Japanese Patent JP6701443
Kind Code:
B2
Abstract:
A signal processing circuit is provided that generates output signals to be output from spatially different output ports based on bit combinations of an input word consisting of a plurality of bit signals. A distributed memory, a ROM and a DAC in which the signal processing circuit is used are also provided. A recognition circuit includes a serial port to which a bit signal is input and 2N output ports recognizing an input N-bit word and corresponding uniquely to 2N bit combinations. Output ports of the recognition circuit are connected to 2N input ports of an electric circuit. With no signal input to the recognition circuit, all outputs are constantly in a Low level state. In a case where a bit signal is input to the serial port of the recognition circuit, only one of the output ports corresponding to the bit combinations turns to a High level state.
Inventors:
Ibrahim Mohammed Salaherdin Ahmed Ezeerdin
Yohei Sakamaki
Nakano Shinsuke
Kota Shika
Yuko Kawajiri
Yohei Sakamaki
Nakano Shinsuke
Kota Shika
Yuko Kawajiri
Application Number:
JP2019513677A
Publication Date:
May 27, 2020
Filing Date:
April 19, 2018
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
H03M9/00; G11C7/10; G11C8/06
Domestic Patent References:
| JP63312656A | ||||
| JP2012027984A | ||||
| JP59219008A |
Foreign References:
| WO2012133519A1 | ||||
| US20070047370 | ||||
| US20090010090 | ||||
| US9235065 |
Attorney, Agent or Firm:
Patent Business Corporation Tani/Abe Patent Office