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Title:
SIGNAL PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JP2010278492
Kind Code:
A
Abstract:

To prevent cumulation of both of quantization errors generated by digital conversion of offset sections and quantization errors generated by digital conversion of data sections.

In a signal processing circuit, the offset section of an analog signal to be processed having an analog value of 10.5 is converted digitally, thus obtaining eleven (11) digital values. A quantization error generated by the digital conversion of the offset section becomes 0.5. When the data section of the analog signal to be processed having an analog value of 20.4 is converted digitally, an analog value of 20.9, which is obtained by adding a quantization error of 0.5 generated by the digital conversion of the offset section, is converted digitally. The data section becomes a digital value of 21. A difference, where a digital value of 11 in the offset section is subtracted from a digital value of 21 at the data section, becomes a value of digital data. The digital value after the digital conversion of the offset section becomes a reference in digital conversion of the data section, thus reducing quantization errors.


Inventors:
WADA SATORU
Application Number:
JP2009126099A
Publication Date:
December 09, 2010
Filing Date:
May 26, 2009
Export Citation:
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Assignee:
FUJIFILM CORP
International Classes:
H04N5/14; H04N5/335; H04N5/369; H04N5/372; H04N5/378
Attorney, Agent or Firm:
Kenji Ushiku
Tadashi Inoue
Takaaki Teiaki



 
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