PURPOSE: To attain the reduction of the sample frequency of a converter by using the sample values of parallel connected A/D converters and performing amplitude control and AGC/VFO control.
CONSTITUTION: By an AGC 1 and a VFO 9, a signal amplitude and a sampling clock phase are controlled using the sampling data of the A/D 6, 7, and a control error at the time of processing a digital signal is reduced. The A/D 6, 7 are connected in parallel, and the even numbered sample data are quantized by the A/D 6 and the odd numbered sample data are quantized by the A/D 7. The sample values of these outputs are selected by the clock CLKP of the output of a frequency divider 14 to be outputted. The sample data timing of the A/D 6 is advanced by one clock of the clock SCLK for the A/D 7. Since the sample data of the A/D 6 are outputted when the CLKP is H and the sample data of the A/D 7 are outputted when the CLKP is L by a selector 8, the sample data are sent successively to the input ends of an amplitude detector 2 and a phase detector 10. Thus, the sampling frequency is reduced.
HIRANO AKIHIKO
IWABUCHI KAZUNORI
YAMAKAWA HIDEYUKI
ISHIDA YOSHITERU
KOSUGE MINORU
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