Title:
信号処理装置及び撮像装置
Document Type and Number:
Japanese Patent JP4323599
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce chip area by installing a specified value detection means having a function outputting the maxim or minimum value signals of plural signal sources and sequentially outputting individual signals from the plural signal sources. SOLUTION: A voltage follower circuit is constituted of differential amplifiers for maximum value/minimum value detection 10 and 11. At necessary time in an accumulation period, the outputs of the differential amplifiers for maximum/minimum values detection 10 and 11 connected to pixels from which maximum/minimum values are to be outputted are connected to a common output line 20 and constant current MOS transistors for maximum/minimum values detection 16 and 17 are made active. Thus, the differential amplifiers for maximum/minimum value detection 10 and 11 are connected to the common output lines 20 and 20' in common by turning on ϕPEAK and ϕBTM. Thus, the output voltage from the pixel outputting the maximum value and the minimum value among the plural pixels is outputted respectively to the common lines 20 and 20'. Individual signals can be outputted sequentially by actively operating the nMOS constant current source 18 of the differential amplifier for minimum value detection 11.
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Inventors:
Hidekazu Takahashi
Application Number:
JP35762098A
Publication Date:
September 02, 2009
Filing Date:
December 16, 1998
Export Citation:
Assignee:
Canon Inc
International Classes:
G02B7/28; G03B13/36; H04N5/335; H04N5/361; H04N5/365; H04N5/369; H04N5/3745; H04N5/378
Domestic Patent References:
| JP3070276A | ||||
| JP1222583A | ||||
| JP3163972A | ||||
| JP3250764A |
Attorney, Agent or Firm:
Keizo Nishiyama
Yuichi Uchio
Yuichi Uchio