Title:
SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP2006060699
Kind Code:
A
Abstract:
To provide a signal processor capable of reducing the using number of PLL circuits.
The signal processor has a reference clock generation circuit 8 which generates a reference clock CLK1 used as synchronous reference of signal processing, a counter 6 which counts the reference clock CLK1, and a frequency control circuit 5a which samples the count value of the counter 6 using an input clock from the outside, compares an incremental value IV from the previous sample value with an expected value, and controls frequency of the reference clock CLK1 according to a comparison result.
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Inventors:
OTOMO GOICHI
Application Number:
JP2004242580A
Publication Date:
March 02, 2006
Filing Date:
August 23, 2004
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H03M7/30; H04N19/00; H04N19/423; H04N19/70
Attorney, Agent or Firm:
Hidekazu Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu