To provide a signal processor capable of reducing unnecessary access waiting time without requiring great reform of architecture or increase in a circuit scale or in a memory cell area for improving signal processing performance when a work memory is shared in the signal processor.

This signal processor is provided with a main device 1, auxiliary devices 2a-2b, a bus 3 connected to the main body 1 to serve as its data transmission path, a first memory 4a connected to the bus 3 and used only by the main device 1, a second memory 4b shared between the main device 1 and the auxiliary devices 2a-2b, and an arbitrator 5 connected between the bus 3, the auxiliary devices 2a-2b, and the second memory 4b to arbitrate access to the second memory 4b.

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