Title:
SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP3840803
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To set the position of a 'start' and an 'end' of a vertical blanking signal, regardless of the number of lines between vertical synchronizing signals.
SOLUTION: An up-counter 3 counts up a count value according to a 2fh clock that is synchronized with a horizontal synchronizing signal, and the value is supplied to one of input terminals of an EX-OR gate 5 and a down-counter 8. The gate 5 outputs data when the count value from the counter 3 coincides with a value from a register 4. The counter 8 counts down a count value, loaded from the counter 3 in the prescribed timing of a vertical synchronizing signal according to the 2fh clock and supplies it to one of input terminals of an EX-OR gate 10. The gate 10 outputs data, when the counter value from the counter 8 matches with a value from a register 9.
Inventors:
Takamine Nagamine
Shinji Takahashi
Shinji Takahashi
Application Number:
JP14416998A
Publication Date:
November 01, 2006
Filing Date:
May 26, 1998
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04N5/06; H04N3/24; H04N3/27; H04N5/46; H04N5/66; (IPC1-7): H04N3/24; H04N3/27; H04N5/06; H04N5/46
Domestic Patent References:
| JP7322089A | ||||
| JP9135411A |
Attorney, Agent or Firm:
Masatomo Sugiura