Title:
SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JPH02295226
Kind Code:
A
Abstract:
PURPOSE: To provide a function for digital D.C. level control by incorporating a DA converter having a circuit connected to an output terminal for selectively offsetting a D.C. level of an output signal from the DA converter. CONSTITUTION: In a picture-in-picture video signal processing system, a digital signal to be converted and a direct-current(D.C.) control value are coupled with a digital-to-analog(DA) converter 24 through a multiplexer 22. A reference potential is coupled with a capacitor 30 at a specific interval at the same time with the D.C. control value coupled with the DA converter 24. At another interval where the digital signal is coupled with the DA converter 24, the output of the DA converter 24 is offset on a D.C. basis by a circuit for selectively offsetting an output signal. Consequently, luminance control can be performed digitally without widening the bit width of the system and lowering the performance.
Inventors:
BAASU ARAN KIYANFUIIRUDO
RATSUSERU TOOMASU FURINGU
RATSUSERU TOOMASU FURINGU
Application Number:
JP9420590A
Publication Date:
December 06, 1990
Filing Date:
April 11, 1990
Export Citation:
Assignee:
THOMSON CONSUMER ELECTRONICS
International Classes:
H03M1/10; H03M1/66; H03M1/70; H04N5/18; H04N7/26; H04N5/45; H04N5/57; H04N11/04; (IPC1-7): H03M1/10; H04N7/13; H04N11/04
Domestic Patent References:
| JPS63185172A | 1988-07-30 | |||
| JPS63160469A | 1988-07-04 |
Attorney, Agent or Firm:
Katsunori Watanabe