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Title:
SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JPS58221435
Kind Code:
A
Abstract:

PURPOSE: To convert parallel data in whole channels by a common P/S (parallel/ serial) converting circuit and to reduce the number of devices, by converting the parallel data into serial data by every bit, then distributing the code-converted data to MODEM in respective channels through a bit memory.

CONSTITUTION: The parallel data are inputted to an asynchronous processing memory 12 in the P/S converting circuit 11, taken out by an internal scanner address 14a of a scanner address generator 14 and inputted to a data selector 15. Subsequently, the parallel data are selected in every bit determined by a bit counter 16 to be converted into serial data. The serial data shaped by code converting circuits 17aW17n are sent to the bit memory 19 and stored in respective channels of the memory 19 which correspond to the positions read out from the memory 12. The stored data are sent to MODEMs 8aW8n by a control signal 20 indicating the units to be transmitted.


Inventors:
KURIMOTO TAKATSUGU
AKIMOTO JIYUNICHIROU
Application Number:
JP10430482A
Publication Date:
December 23, 1983
Filing Date:
June 17, 1982
Export Citation:
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Assignee:
MEIDENSHA ELECTRIC MFG CO LTD
International Classes:
H03M9/00; G06F13/00; G06F13/38; H04L29/02; (IPC1-7): G06F3/04; G06F5/04; H03K13/256
Domestic Patent References:
JPS556957A1980-01-18
Attorney, Agent or Firm:
Fujiya Shiga



 
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