PURPOSE: To detect the bit error of a normal transmission line with a parity bit by sending the parity bit from a transmission side equipment together with parallel data, applying parity check at a reception side equipment and controlling a latched timing.

CONSTITUTION: N-bit parallel data are inputted to the parallel input terminals P1-Pn of the transmission side equipment 101 and also inputted to a parity generating circuit 1. The parity generating circuit 1 identifies an n-bit level and generates the parity bit (data 11). A parallel output in (n+1)-bit from the latch circuit 6 is inputted to a parity check circuit 7, where the parity is checked. A counter 8 counts clocks inputted to a clock terminal C and outputs a pulse at every (n+1)-bit when the signal of parity error is not inputted to a set terminal S and outputs a pulse at every n-bit or (n+2)-bit when no error signal is inputted.