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Title:
SIGNAL TRANSMITTER-RECEIVER
Document Type and Number:
Japanese Patent JPH0265318
Kind Code:
A
Abstract:

PURPOSE: To simplify circuit constitution by selecting a data signal, which is inputted to a selector in a transmitting side, and a delayed clock signal with a clock signal which is not delayed, transmitting the data signal and clock signal and latching the delayed clock in a receiving side.

CONSTITUTION: In a transmitting side device, a data signal (a) and a clock signal (b), whose phase is coincident with that of the signal (a), of a period T are inputted to the selector according to a signal (c) which is delayed by the 1/4 or 3/4 period T in a delay circuit 1. The selector selects the signal (a) or (c) in correspondence to the level of the clock signal (b), which is not delayed, and a signal (d) is sent to a transmitting path. The signal (d) includes a rising point in a block, which is half of the period, and includes the data signal in the remaining hair block. In the receiving side, the transmitted signal (d) is inputted to a terminal D of an FF4 and the rising point of a clock signal (e), which is delayed only by T/2 in a delay circuit 2, is inputted to a clock terminal C of the FF4. Then, sent signal data before the delay are latched. Thus, the circuit constitution is simplified.


Inventors:
OIKAWA YOSHINORI
Application Number:
JP21516688A
Publication Date:
March 06, 1990
Filing Date:
August 31, 1988
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03M5/06; H04L25/49; (IPC1-7): H03M5/06; H04L25/49
Attorney, Agent or Firm:
Namio Akio (1 person outside)



 
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