Title:
SIMULATING METHOD, SIMULATOR, RECORDING MEDIUM HAVING RECORDED SIMULATION PROGRAM, AND MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3660137
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a simulator capable of exactly simulating the electric characteristics of a semiconductor device.
SOLUTION: Means 73 for calculating the electric characteristics of elements in a device simulator 70 comprises at least a lattice generating means 51, a linear quasi-Fermi potential setting means 52, a bias setting means 53, a coefficient matrix and residual vector setting means 54, and a matrix calculating means 55. The lattice generating means 51 sets a finite number of lattice points in and around a semiconductor device to generate a plurality of lattices. The linear quasi-Fermi potential setting means 52 sets a linearly changing quasi- Fermi potential of carriers in the generated lattices. The bias setting means 53 inputs a bias to be applied to specified electrode regions. The coefficient matrix and residual vector setting means 54 obtains the carrier density a point in each of the lattices from the quasi-Fermi potential to set a coefficient matrix and residual vector for a fundamental equation. The matrix calculating means 55 calculates the coefficient matrix to obtain a soln.
Inventors:
Toshiyuki Toda
Application Number:
JP27218098A
Publication Date:
June 15, 2005
Filing Date:
September 25, 1998
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F9/44; G06F17/50; H01L29/00; (IPC1-7): H01L29/00; G06F9/44
Domestic Patent References:
| JP2800437B2 | ||||
| JP6139320A |
Attorney, Agent or Firm:
Hidekazu Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Iwa Saki Kokuni
Kawamata Sumio