Title:
SIMULATION APPARATUS AND PROGRAM
Document Type and Number:
Japanese Patent JP2009026113
Kind Code:
A
Abstract:
To provide a simulation apparatus that can quickly and accurately verify concerted operation of software and hardware.
A scheduling means implemented by a pseudo OS 11 and a pseudo CPU 12 in a framework 10 schedules the execution of software SW to be verified. A communication means 13 establishes communication between hardware models HW1 to HWn and the software SW to be verified. An execution release means implemented by the pseudo OS 11 and pseudo CPU 12 releases the execution right to a scheduler 20 according to the execution schedule of the software SW to be verified.
Inventors:
SAKAMOTO YOSHINORI
TANIMIZU TOSHIYUKI
MATSUBAYASHI FUYUKI
KUGE RYO
YOSHINO TATSUYA
MIYAKE HIDEO
KIMURA MASAHARU
MATSUMOTO SUKENORI
TANIMIZU TOSHIYUKI
MATSUBAYASHI FUYUKI
KUGE RYO
YOSHINO TATSUYA
MIYAKE HIDEO
KIMURA MASAHARU
MATSUMOTO SUKENORI
Application Number:
JP2007189317A
Publication Date:
February 05, 2009
Filing Date:
July 20, 2007
Export Citation:
Assignee:
FUJITSU MICROELECTRONICS LTD
TOPS SYSTEMS KK
TOPS SYSTEMS KK
International Classes:
G06F11/28; G06F17/50
Domestic Patent References:
| JP2003036284A | 2003-02-07 | |||
| JP2004234528A | 2004-08-19 | |||
| JP2005182359A | 2005-07-07 | |||
| JP2004348291A | 2004-12-09 | |||
| JP2005018623A | 2005-01-20 |
Attorney, Agent or Firm:
Takeshi Hattori