PURPOSE: To attain high speed processing by utilizing the result of verification of a low-order logical block to verify the function of a logical block of high- order, thereby decreasing the time required for the verification.

CONSTITUTION: The storage content of a circuit state storage device 1 storing the circuit state of a logical circuit to be simulated is fed to an operating device 2 as required. The operating device 2 decodes connecting information fed from a connecting information storage device 3 as an instruction and simulates a logical element. Then the simulation of the gate level is operated sequentially by an instruction counter 4 and an instruction address kew 5. A logical function storage device 6 added thereto stores an output state value to an input state value to the logical block in executing the simulation of the low-order logical block comprising plural logical gates, receives the output of the operating device 2 as an address and returns the corresponding storage content.