Title:
SIMULATION SYSTEM FOR PARALLEL LOGIC TYPE LANGUAGE
Document Type and Number:
Japanese Patent JPH01175038
Kind Code:
A
Abstract:
PURPOSE:To execute simulation by a sequential processing type by preventing execution processing information from flowing out during the invariable period of a cycle counter to be counted up every circulation and restart of the internal processing of each processor in a queue held in a simulator. CONSTITUTION:The system is provided with the counter to be counted up every circulation of the internal processing of the processor in the queue held in the simulator and restart of the internal state of the same processor and a means for suppressing the outflow of information relating to processing to be executed during the no change of the counter value to another processor. A common variable in the processor is converted into a format including two counters having a referable cycle for knowing the value and a realized cycle obtained after realizing the initially appearing variable. A dispersing unification for setting up a value for a common variable uses a referable cycle value in a self-processor as an execution cycle value and adds to the realized cycle value to be used by respective processors in common.
Inventors:
OOHARA YURI
TORII SATORU
ISHIZAKI AKIKO
OIKAWA SAORI
ONO MIYUKI
TORII SATORU
ISHIZAKI AKIKO
OIKAWA SAORI
ONO MIYUKI
Application Number:
JP17949687A
Publication Date:
July 11, 1989
Filing Date:
July 17, 1987
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F15/16; G06F9/44; G06F9/52; G06F15/177; (IPC1-7): G06F9/44; G06F15/16
Attorney, Agent or Firm:
Sadaichi Igita