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Patent Searching and Data


Title:
SIMULATOR
Document Type and Number:
Japanese Patent JPH0528212
Kind Code:
A
Abstract:

PURPOSE: To increase simulation speed by accumulating a test signal in an event memory in the case of a chip executing a static operation and outputting a selective signal so that the same test signals are not read out repeatedly.

CONSTITUTION: The event memory 5 accumulates the test signals in the memory by the selective signal from a memory controller 1 and outputs the test signal in the memory or outputs the test signals without accumulating them in the memory. The test signal from the event memory 5 is inputted to a real chip packaged on a chip packaging substrate 6, and an output signal from the real chip is inputted to a simulation part 7. It simulates a circuit part consisting of a software model except for a real chip part by the test signal from a test signal generation circuit 4 and the output signal from the real chip.


Inventors:
KATO KEIICHI
Application Number:
JP17863191A
Publication Date:
February 05, 1993
Filing Date:
July 19, 1991
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F11/26; G06F15/60
Attorney, Agent or Firm:
Uchihara Shin