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Title:
SIMULATOR
Document Type and Number:
Japanese Patent JPS61184472
Kind Code:
A
Abstract:

PURPOSE: To perform the simulation of a multiphase clock, by using memory for storing an event and an event mask, a node counter for outputting the node number of an element and a phase counter for showing the phase during practice.

CONSTITUTION: An access circuit 5 uses a node counter 3 to access event memory 1 and simultaneously uses the node counter 3 and a phase counter 4 to access an event mask memory 2. Further, the access circuit 5 inputs an event access value 101 and a phase mask value 102 and performs simulation when the event access value 101 shows the presence of an event and is not masked by the phase mask value 102 to issue event reset 103 to an event 1 to distinct the same. If the event access value 101 is masked by the phase mask value 102, said access circuit 5 performs nothing and outputs a count-up signal 104 in order to perform the next access to transfer to the next event processing.


Inventors:
KOIKE MASAHIKO
Application Number:
JP2477385A
Publication Date:
August 18, 1986
Filing Date:
February 12, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
G01R31/28; G06F11/26; G06F17/50; H03K19/00; G06F19/00; (IPC1-7): G01R31/28; H03K19/00
Attorney, Agent or Firm:
Shinsuke Ozeki



 
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