Title:
SINGLE CHIP MICROCOMPUTER
Document Type and Number:
Japanese Patent JP2739573
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent malfunction in a single chip microcomputer having an external synchronizing signal.
SOLUTION: The external synchronizing signal E formed in an internal clock generation circuit 11 is outputted to an external terminal 275 through a gate means 12. A control signal C corresponding to a setting state is supplied to the control terminal of the gate means 12 from a control register 15 to which data can be set by a microprocessor, and the external synchronizing signal E is controlled to be not outputted to the external terminal 23. Thus, the output of the external synchronizing signal E to the external terminal (pin) can be inhibited in a single chip mode.
Inventors:
Haruo Keida
Takashi Tsukamoto
Nobutaka Nagasaki
Takashi Tsukamoto
Nobutaka Nagasaki
Application Number:
JP24280196A
Publication Date:
April 15, 1998
Filing Date:
September 13, 1996
Export Citation:
Assignee:
株式会社日立製作所
株式会社日立マイコンシステム
株式会社日立マイコンシステム
International Classes:
G06F15/78; (IPC1-7): G06F15/78
Domestic Patent References:
| JP60129820A | ||||
| JP6045828A | ||||
| JP55135960A | ||||
| JP575164A | ||||
| JP5537649A | ||||
| JP5840643A | ||||
| JP55150028A |
Attorney, Agent or Firm:
Tomio Ohinata