PURPOSE: To improve the data transmission efficiency with a single chip microcomputer by setting a transmission error detecting circuit into a serial interface to detect the errors at transmission of data.

CONSTITUTION: A transmission error detecting circuit 15 consisting of an exclusive OR gate (EOR gate) 92 and an AND gate 93 is added to a serial interface 9. At transmission of the serial data, a control circuit 91 sets a transmission mode signal 124 at 1 and therefore the output of the gate 92 is set at 1 only when no coincidence is obtained between a level set on a transmission line and the output of a shift register 122, i.e., at a transmission error. Therefore the output of the gate 93 is set at 1 at a transmission error only for a period when an output pulse 129 of a Baud rate generator BRG123 is kept at 1. Thus a transmission error signal 94 is set at 1 and sent to a CPU. As a result, a transmission error is detected in real time and the CPU performs the error processing at an early stage. Then the data transmission efficiency is improved.