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Title:
SINGLE CHIP MICROCOMPUTER
Document Type and Number:
Japanese Patent JPS63118948
Kind Code:
A
Abstract:

PURPOSE: To generate plural arbitrary time intervals with a timer, by starting up a specific microprogram by a signal being generated by an incorporated time base.

CONSTITUTION: A time base 13 outputs a request signal at every 1/220sec to a signal line 14. A CPU control part 6 detects the request signal in a final machine cycle executing at that time, and starts an automatic frequency division processing. At this time, since a program counter 3, a universal register group 9, and a PSW register 16 are not used in the automatic frequency division processing, no saving is performed. The automatic frequency division processing, by reading out the value of an automatic frequency division processing point 15, and outputting it to an address bus 1, selects counter registers 12-1W12-4 in which prescribed values are set in advance, and subtracts 1 from respective value. When either the registers 12-1W12-4 goes to '0' as the result of subtraction, an interruption acceptance processing is executed successively.


Inventors:
SAKAMOTO HIDEKI
MATSUSHIMA OSAMU
Application Number:
JP26585786A
Publication Date:
May 23, 1988
Filing Date:
November 07, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F9/48; G06F1/14; G06F15/78; (IPC1-7): G06F9/46; G06F15/06
Domestic Patent References:
JPS51120640A1976-10-22
JPS5429537A1979-03-05
JPS6073748A1985-04-25
JPS61259320A1986-11-17
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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