Title:
標的の画像化に用いるシングルチップかつノイズ耐性の1次元CMOSセンサ
Document Type and Number:
Japanese Patent JP2007522539
Kind Code:
A
Abstract:
A linear sensor array for imaging coded indicia includes an analog front end and a digital back end integrated on a single CMOS chip. A real-time, correlated double sampling circuit is used for noise suppression.
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Inventors:
Carlson, Bradley
Yang, May
Yang, May
Application Number:
JP2006545736A
Publication Date:
August 09, 2007
Filing Date:
December 07, 2004
Export Citation:
Assignee:
Symbol Technologies, Inc.
International Classes:
G06K7/01; G06K7/10; G06T1/00; H04N1/028; H04N3/00; H04N5/353; H04N5/361; H04N5/363; H04N5/365; H04N5/374; H04N5/378
Domestic Patent References:
| JP2003273343A | 2003-09-26 | |||
| JP2002209143A | 2002-07-26 | |||
| JP2000235615A | 2000-08-29 | |||
| JP2003132301A | 2003-05-09 | |||
| JPH1065971A | 1998-03-06 | |||
| JP2002232787A | 2002-08-16 | |||
| JPS57166672A | 1982-10-14 |
Foreign References:
| WO2003069897A1 | 2003-08-21 |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita