Title:
SINGLE-PHASE CHARGE TRANSFER DEVICE
Document Type and Number:
Japanese Patent JPS57164567
Kind Code:
A
Abstract:
A uniphase, buried-channel, semiconductor charge transfer device wherein a portion of each cell includes an inversion layer, or "virtual electrode" at the semiconductor surface, shielding that region from any gate-induced change in potential. Each cell is comprised of four regions (I, II, III, IV) wherein the characteristic impurity profile of each region determines the maximum potential generated therein for the gate "on" and gate "off" conditions. Clocking the gate causes the potential maxima in regions I and II to cycle above and below the fixed potential maxima in regions III and IV beneath the virtual electrode. Directionality of charge transfer is thereby achieved, since the potential maximum for region II ( phi maxII) remains greater than for region I ( phi maxI) and phi maxIV> phi maxIII, for both gate conditions. A self-aligned process for fabrication is provided, including a number of ion implant stages to fix the required impurity profiles in each cell for generating the correct potential profiles for charge propagation. CCD imagers, memory devices, an analog processors are contemplated systems wherein the invention is to be implemented.
Inventors:
YAROSURABU HINESEKU
Application Number:
JP2582682A
Publication Date:
October 09, 1982
Filing Date:
February 19, 1982
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L29/762; G11C19/28; G11C27/04; H01L21/339; H01L21/8234; H01L27/148; H01L29/423; H01L29/76; H01L29/768; H01L29/772; (IPC1-7): H01L29/76