Title:
スレーブ側デバイス
Document Type and Number:
Japanese Patent JP7269610
Kind Code:
B2
Abstract:
To provide a slave side device that connects, in M stages, clock-synchronized serial data receiving circuits that convert serial data of a reference bit number into parallel data, and performs conversion into parallel data of "reference bit number×M".SOLUTION: First and second clock synchronous serial data receiving circuits 1A and 1B are mounted on first and second sockets 21 and 22 of a bus system 2 provided in a slave side device 402, respectively, and when a 16-bit length (twice the number of reference bits) serial data signal SD, select signal SEL, and serial clock signal SCK are input from a master side device 401, the first to eighth bits are output from output signal line L6B of the second clock synchronous serial data receiving circuit 1B, and the ninth to 16th bits are output from the output signal line L6A of the first clock synchronous serial data receiving circuit 1A, and 16-bit parallel data can be obtained.SELECTED DRAWING: Figure 5
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Inventors:
Hiroyuki Sakamoto
Yuji Takahashi
Yuji Takahashi
Application Number:
JP2022025211A
Publication Date:
May 09, 2023
Filing Date:
February 22, 2022
Export Citation:
Assignee:
Japan ID Co., Ltd.
PA Net Technology Laboratory Co., Ltd.
NAC Planning Co., Ltd.
PA Net Technology Laboratory Co., Ltd.
NAC Planning Co., Ltd.
International Classes:
H04L25/40; G06F13/38; H03M9/00; H04L7/00
Domestic Patent References:
| JP2011197981A | ||||
| JP2015142244A | ||||
| JP2005050153A | ||||
| JP8185363A |
Attorney, Agent or Firm:
Shinichi Fukuda