Title:
スマートカード
Document Type and Number:
Japanese Patent JP4163264
Kind Code:
B2
Abstract:
The memory card comprises a counter region consisting of at least two levels of counters of at least two bits each which may be used on an abacus principle. A first indicator region consists of at least two indicator registers. Each register has at least two bits, serving to display the effective erasure of the counters. There is also a balance region accessible for reading and writing. It is only erasable if the contents of the counter region have been incremented. A second indicator region is structured in two fields associated with the balance region. Writing of the balance bits takes place simultaneously in the balance region and in the second indicator region. The balance region and the second indicator region each comprise a validation bit allowing determination of whether the present balance is completely written.
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Inventors:
Marshall Menconi
Application Number:
JP10820596A
Publication Date:
October 08, 2008
Filing Date:
April 26, 1996
Export Citation:
Assignee:
FRANCE TELECOM
International Classes:
G06K19/073; G11C17/00; G06K17/00; G06K19/00; G07F7/08; G07F7/10; G11C5/00; G11C16/02; H04M15/00; H04M17/00
Domestic Patent References:
| JP7110876A | ||||
| JP3241463A | ||||
| JP3008090A |
Foreign References:
| FR2689662A1 | ||||
| FR2701578A1 | ||||
| FR2698468A1 |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro