Title:
SMEAR CORRECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS62137979
Kind Code:
A
Abstract:
PURPOSE:To perform smear correction with high precision by allowing an image pickup signal, which is outputted one field ahead of a smear component obtained in a vertical ineffective period, to pass a delay circuit to solve the lag. CONSTITUTION:The output from a solid-state image sensor 1 is supplied to an A/D converter 4 through a sampling and holding circuit 2, etc., and is converted to a digital signal. This signal is supplied to a field memory 5, and an image pickup signal So outputted in a vertical effective period Ta is written successively and is read and outputted successively after the period corresponding to one field. The digital signal is supplied to a line memory 8 through an adder 7, and a smear component Sm outputted in a vertical ineffective period Te is written. The image pickup signal So is supplied to a subtractor 9, and contents of the line memory 8 are read out and are supplied to the subtractor 9 through a gain control circuit 10. Thus, an image pickup signal S deg.' where the smear component Sm is eliminated is obtained from the subtractor.
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Inventors:
ONGA MAKOTO
KONDOU NORIAKI
KONDOU NORIAKI
Application Number:
JP27976585A
Publication Date:
June 20, 1987
Filing Date:
December 12, 1985
Export Citation:
Assignee:
SONY CORP
International Classes:
H04N9/07; H04N5/335; H04N5/341; H04N5/347; H04N5/359; H04N5/3725; H04N5/3728; H04N5/374; H04N5/378; (IPC1-7): H04N5/335; H04N9/07
Attorney, Agent or Firm:
Sada Ito