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Title:
SOFTWARE CONFIGULATION SYSTEM
Document Type and Number:
Japanese Patent JPH04243406
Kind Code:
A
Abstract:

PURPOSE: To reduce power consumption by inserting an instruction while temporarily holding an address bus and a data bus in a program as to a system in which a required program operation is executed with a battery power source.

CONSTITUTION: In a timer module for a main routine, a timer value is set in a memory in a step A1 and whether or not the timer value is '0' is judged in a step A2. When the value is not '0', a CPU executes an instruction for temporarily holding the address bus or the data bus at low or high level, such as meaningless division instruction or multiplication instruction, in a step A7, and then the step A2 is conducted. Such processing is repeatedly executed until the timer value reaches '0', and when it reaches '0', the timer module is completed in a step A3.


Inventors:
KOMATSUDA SEIJI
Application Number:
JP1568391A
Publication Date:
August 31, 1992
Filing Date:
January 17, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F1/32; G06F9/30; (IPC1-7): G06F1/32; G06F9/30
Attorney, Agent or Firm:
Yu Sanada



 
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