PURPOSE: To improve the S/N ratio and the circuit integration, by providing an impurity diffusion regions one of which is connected to a signal line in the direction of arrangement adjacent to a selecting gate every other respectively and the other of which is connected to a drain, for decreasing the vertical smear.

CONSTITUTION: Picture element regions 111∼1112 are arranged on a semiconductor substrate 10 and address gates AG1∼AG12 are provided to the regions and a vertical shift register 18 selecting successively the gates is connected to the gates. Impurity diffusion regions S1∼S3, D1∼D4 are provided at the outside of selecting gates G1∼G12, the regions S1∼S3 are connected to a vertical signal line 13, and the regions D1∼D4 are connected to a drain line 14. Thus, gates G1, G4, G5, G8, G9, G12 provided at ends of a charge transfer line 12 and the D1∼ D4 function as the drain selecting gates and the gates G2, G3, G6, G7, G10 G11 provided at the regions S1∼S3 and the end of the charge transfer line 12 function as the signal selecting gates.