To prevent reverse flow of signal charges when a CCD is reset by controlling a timing of a transfer clock pulse and a reset clock pulse.

A horizontal transfer register 1 is formed on an n-channel imbeded channel region 15 and a horizontal output gete section 6 is formed on the n-channel imbeded channel region 15. A reset gate section 11 is formed between an n-channel region between a floating diffusion region 7 and a reset drain region 10. Then the rising of a reset pulse given to the reset gate section 11 is set faster than the rising of a transfer clock pulse given to a transfer section 3 at a final stage.