To read image data from one pixel array at a plurality of frame rates at the same time so that image data read specially from a pixel group with a low resolution may have a high frame rate.
A pixel array 10 is divided into first and second pixel groups having different resolutions. Vertical scanning circuits 21 and 22 vertically scan the first and second pixel groups according to vertical synchronization signals VD1 and VD2, respectively. CDS circuits 31 and 32 read an image data for one line which is selected from the first and second pixel groups through vertical scanning by the vertical scanning circuits 21 and 22, and temporarily hold it. Horizontal scanning circuits 41 and 42 horizontally scan the CDS circuits 31 and 32 according to horizontal synchronization signals HD1 and HD2, so as to sequentially output the image data for one line held by the CDS circuits 31 and 32 from the CDS circuits 31 and 32.
KANBE KOICHI
IWAMOTO TSUYOSHI
| JP2005295381A | 2005-10-20 | |||
| JP2005277513A | 2005-10-06 | |||
| JP2007124137A | 2007-05-17 | |||
| JP2006303755A | 2006-11-02 | |||
| JP2008042305A | 2008-02-21 | |||
| JPH0937156A | 1997-02-07 |
Masataka Otani
Satoshi Sakurai