Title:
SOLID-STATE IMAGING DEVICE
Document Type and Number:
Japanese Patent JP2022172710
Kind Code:
A
Abstract:
To provide a solid-state imaging device capable of improving an insulating breakdown voltage of a transistor formed by adopting a fin type structure.SOLUTION: A solid-state imaging device includes a first semiconductor layer, a transistor, and an electric field relaxation section. The transistor includes: a fin that is erected on a primary surface portion of the first semiconductor layer; a first main electrode, a channel formation region, and a second main electrode that are disposed on the fin along a channel lengthwise direction; and a gate insulation film and a gate electrode that cover a top surface and side surfaces of the fin so as to extend over the fin along a channel width direction. The electric field relaxation section is disposed on a bottom part of a side surface of the fin, and relaxes electric field concentration.SELECTED DRAWING: Figure 1A
More Like This:
| WO/1998/026455 | DEVICE AND PROCESS FOR READING A PHOTONIC DETECTOR MATRIX |
| JP2010010740 | IMAGE SENSOR |
| JP2008506341 | Dual panel pixel readout device in the imaging device |
Inventors:
EBIHARA YASUHIRO
Application Number:
JP2021078800A
Publication Date:
November 17, 2022
Filing Date:
May 06, 2021
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP
International Classes:
H01L27/146; H01L21/8234
Attorney, Agent or Firm:
Patent Attorney Corporation Tsubasa International Patent Office