Title:
SPECULATIVE EXECUTION INSTRUCTION EXCEPTION CONTROL SYSTEM
Document Type and Number:
Japanese Patent JP3452246
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To easily realize the exact (under the consideration of the order of instruction executions) preservation of the executed states of speculative execution instructions after the generation of any exception.
SOLUTION: An arithmetic exception buffer 28 is provided with an entry in each branch level to be applied and updated by a branch level controlling means 100, and an ROB registration number and exception classification information is held in each entry, and the information of the oldest instruction among exception generation instructions in each branch level is registered in each entry by comparison controlling parts 44-47. When an instruction in an ROB 29 instructed by an RPTR 31 can be retired, a reducing means 200 compares the ROB registration number of the instruction with the ROB registration number in an entry e0 in the arithmetic exception buffer 28 at that point of time, and when they are made coincident, the reducing means 200 reduces the update of a software visible register 12 related with the following instructions of the instruction. An exception classification information holding means 400 obtains and holds exception classification information in an Int0 storage part 40 according to the reduction.
Inventors:
Hisao Koyanagi
Application Number:
JP26440999A
Publication Date:
September 29, 2003
Filing Date:
September 17, 1999
Export Citation:
Assignee:
NEC
International Classes:
G06F9/38; (IPC1-7): G06F9/38
Domestic Patent References:
| JP756760A | ||||
| JP11184696A |
Attorney, Agent or Firm:
Junichi Kawahara