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Title:
SPEED DETECTION CIRCUIT USING MULTIPOLAR RESOLVER
Document Type and Number:
Japanese Patent JPS6267459
Kind Code:
A
Abstract:

PURPOSE: To obtain a speed detection signal at low ripple voltage, by providing two digital type monostable circuits in a speed detection circuit using a multipolar resolver while a bridge circuit comprising a resistance and an FET switch is interposed.

CONSTITUTION: Digital monostable circuits 2 and 2' triggered by an output signal A of a frequency divider 10 and an inversion signal A thereof, each counting pulses of 4.608MHz up to 1024 and output signals B and C, at high-level during the counting and at low-level after the counting. Then, as the signals B and C are of a TTL level, to drive an FET switch, a level conversion is performed to turn the high-level signals B and C into a voltage Vp and the low-level ones into a voltage VN. When switches 13 to 16 made up of FETs are driven by signals B' and C' thus converted in the level, the switches 13 and 15 are turned On and those 14 and 16 OFF according to the level of the signals B' and c'. Thus a differential effect due to a bridge circuitry of the switches 13 to 16 turns a speed detection signal into a low ripple.


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Inventors:
SAWA TOSHIHIRO
MATSUMURA TSUKASA
YAMADA KENJI
KUCHIWAKI KAZUHIRO
Application Number:
JP20782385A
Publication Date:
March 27, 1987
Filing Date:
September 20, 1985
Export Citation:
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Assignee:
YASKAWA DENKI SEISAKUSHO KK
International Classes:
G01P3/44; H02P3/06; (IPC1-7): G01P3/44; H02P3/06
Domestic Patent References:
JPS58182559A1983-10-25
JPS59148871A1984-08-25
Attorney, Agent or Firm:
Kazuo Sato



 
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