To efficiently execute fast extraction of square root processing with the addition of a relatively small scale hardware by dividing a square number into plural parts and executing processing extracting partial square root through parallel processing in each part partially several times.

A number to be extracted is set to a number to be extracted part 61. For instance, when the number to be extracted is 16 bits, the number to be extracted is delimited into 4 bits each, and a partial square root calculating device which has two subtracting devices 64 to 67 that are serially connected repeats processing that calculates a 2-bit partial square root through parallel processing to each 4-bit data four times. The square root of numbers to be extracted is calculated by synthesizing partial square roots which are calculated in each processing. Thus, for example, two subtracting devices are needed to double an arithmetic speed, and it is possible to accomplish the improvement of an equivalent arithmetic speed with increase of fewer hardware scales in comparison with a conventional square root extraction of arithmetic unit.