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Title:
SQUELCH CIRCUIT
Document Type and Number:
Japanese Patent JPH0330507
Kind Code:
A
Abstract:

PURPOSE: To prevent the malfunction of a relative equipment to input a receiving signal by providing a fault detecting circuit to detect the defective state of a noise detector and suppressing the output of a reception demodulating signal by this detecting circuit even when the noise detector breaks down.

CONSTITUTION: At first, when a noise detector 1 is normally operated, the output suppression control of the reception demodulating signal is executed by the output of a noise level decider 2. When noise quantity is small, '0' (in the case of positive logic) is outputted to an inhibit circuit 3 and the reception demodulating signal is outputted from the inhibit circuit 3 as it is. When the noise quantity is large, '1' is outputted to the inhibit circuit 3 and the reception demodulating signal is suppressed and not outputted from the inhibit circuit 3. Then, squelch function is presented. On the other hand, when the noise level decider 2 decides that the noise quantity is small (0) and an AGC level decider 4 decides the deteriorating state of a radio wave line, a squelch logic circuit 5 decides that the noise detector 1 is in the defective state. Then, '1' is outputted from the squelch logic circuit 5.


Inventors:
NAKAI KAZUMOTO
Application Number:
JP16389289A
Publication Date:
February 08, 1991
Filing Date:
June 28, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03H7/01; H04B1/10; (IPC1-7): H03H7/01; H04B1/10
Domestic Patent References:
JP58111536B
Attorney, Agent or Firm:
Kihei Watanabe