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Title:
SQUELCH CIRCUIT
Document Type and Number:
Japanese Patent JPS5521674
Kind Code:
A
Abstract:

PURPOSE: To mitigate the feeling of unpleasant to the viewers, by rejecting the signal deterioration specific to digital system caused by the occurrence of abnormity with the squelch circuit in the digital transmission of TV and audio signal.

CONSTITUTION: The digital signal 11 of TV or audio signal fed to the input terminal 1 is fed to the decoder 2 and the error detection circuit 3, and the signal 12 decoded with the decoder 2 is fed to the clamp circuit 8. Further, the error of the signal 11 detected at the circuit 3 is fed to the counter 4 to count the error every given period. The output counted is fed to the comparators 5 and 6 and they are compared with the set threshold values K1 and K2. When the count value of the comparator 5 exceeds the threshold value K1, the set pulse S is generated and if the count value of the comparator 6 is less than the threshold value K2, the reset pulse R is produced. The set and reset pulses S and R are fed to FF7, the output of FF7 is fed to the circuit 8 to clamp the decoding signal 12, allowing to reject the deterioration of code specific to digital system.


Inventors:
IINUMA KAZUMOTO
Application Number:
JP9518178A
Publication Date:
February 15, 1980
Filing Date:
August 03, 1978
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H04L1/00; H03G3/20; H04B1/10; (IPC1-7): H04B1/10; H04L1/00
Domestic Patent References:
JPS4966012A1974-06-26
JPS5111507A1976-01-29



 
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