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Title:
STABILIZED BIAS CIRCUIT
Document Type and Number:
Japanese Patent JPS5983407
Kind Code:
A
Abstract:

PURPOSE: To ensure satisfactory working of a stabilized bias circuit despite a big reduction of the power supply voltage by using a bias circuit which has stable working when the power supply voltage is dropped.

CONSTITUTION: Constant current transistors (TR) 51 and 52 are added to a differential amplifier consisting of TRs 9 and 10 to avoid a change of the current flowing to TRs 9 and 10 despite a change of the power supply voltage. A stabilized bias circuit 50 applies a constant level of bias voltage to the bases of TRs 51 and 52 despite the change of the power supply voltage and consists of a starting resistance 61, TRs 63∼69, diodes 62∼71, etc. When a current flows to the diode 67 after the TR63 is turned on, TRs 68 and 69 are activated. Then the current of the TR68 flows to the diode 70, and half the current of the diode 70 flows to the TRs 64 and 65. As a result, a stable current of the same level as that flowing to the diode 70 flows to the TR69. Thus a stable bias is supplied to TRs 51 and 52 respectively.


Inventors:
OOKUBO TSUNEO
Application Number:
JP19410682A
Publication Date:
May 14, 1984
Filing Date:
November 04, 1982
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03F1/30; G05F1/56; (IPC1-7): G05F1/56; H03F1/30
Domestic Patent References:
JPS55611A1980-01-07
Attorney, Agent or Firm:
Akira Kobiji (2 outside)